1. Field of the Invention
The present invention relates, in general, to socalled micrologic circuits, that is logic circuits made by the integrated circuit technique "condensing" a large number of basic and complex logic functions (logic circuitry) into a single monolithically integrated semiconductor device, according to LSI (Large Scale Integration) of VLSI (Very Large Scale Integration) techniques. According to such techniques a large number of logic elements, including complex ones such as binary decase counters, shiftregister, etc., may be implemented onto a single chip.
More in particular, the invention relates to CMOS logic circuit, i.e. integrated circuits made by the socalled complementary MOS (Metal Oxide Semiconductor) technology, utilizing P-channel and N-channel superficial field effect transistors.
CMOS circuits have the great advantage of dissipating "power" only during transition of internal and input and/or output electrical signals. In other words, if DC levels are applied to a CMOS circuit, the circuit, even though correctly supplied, shows a current absorption (defined as I.sub.CC =quiescent supply current or rest current) which is equal only to the leakage current of internal junctions of the reverse biased circuit. For SSI (Short Scale Integration) and MSI (Medium Scale Integration) CMOS circuits, i.e. with a total number of transistors which may reach about 500, the I.sub.CC current, under rest conditions, i.e. under static conditions of the signals applied to the inputs (with logic levels of 0 or 1 satisfying the limits of the logic levels V.sub.IL and V.sub.IH) is in the order of EQU I.sub.CC =10.sup.-6 A=1 .mu.A
In more densly packed integrated CMOS circuits of modern LSI or VLSI technologies, such a value may even be reduced by two or three orders of magnitude at room temperature so that the stand-by current, or quiescent current, is only fire nanoamperes (nA). As it is easily appreciated, such characteristic makes the CMOS micro-logics extremely advantageous with respect to other families of micrologics and particularly with respect to the one which, because of its extraordinary high speed characteristics, has dominated the field of standard logics (basic logic functions constituting the "connecting tissue" or "binder" for aggregating over complex cards LSI or VLSI integrated micrologic devices): that is, the TTL family (Transistor-Transistor Logic). Such TTL micrologics have in fact the disadvantage of a quiescent current which may vary between few hundreds of microamperes (.mu.A) to few milliamperes (mA).
On the other hand, today many apparatus and/or logic devices made by the CMOS technology are often designed so as to be interfaceable with the output of TTL logic gates. In these instances, the CMOS circuitry is also known as HCT micrologics (from High Speed CMOS, TTL Compatible). In these situations the gate, i.e. the input stage of the HCT logic, must be capable of accepting and discriminating the worst output levels available from a TTL logic output gate, that is:
1 (TTL logic) equivalent to V.sub.OHTTLmin =2.4 V PA1 0 (TTL logic) equivalent to V.sub.OLTTLmax =0.4 V with a sufficient noise immunity, so that: PA1 V.sub.INHmin =2.0 V and V.sub.INLmax =0.8 V. PA1 SW1: ON PA1 SW2: OFF PA1 SW1': OFF PA1 SW2': ON PA1 t1 is the delay introduced by the compatibility interface stage TTL/CMOS; PA1 t2 is the delay introduced by the inverter (IN) for resetting the correct phase of the signal; PA1 t3 is the delay introduced by the switch SW1; and PA1 t4 is the delay introduced by the inverter IN1.
Under these conditions, the triggering threshold voltage for which the input stage of the CMOS logic circuit is designed equals to: EQU (2.0+0.8)/2=1.4 V
This is obtained in practice by providing a suitable input interface stage in order to ensure the necessary compatibility among signals coming from TTL circuits and the CMOS circuitry.
In order to avoid problems of erratic transitions at the equilibrium of the inputs, a voltage hysteresis is implemented in order to force an unbalance of the input reference voltages.
Furthermore in many applications, data coming from TTL logics are samples and stored within the CMOS circuitry under frequency control by a system clock. That is, the TTL logic data are sampled in accordance with the clock pulses of a system clock.
2. Discussion of the Prior Art
According to the prior art, at an input of a CMOS logic circuit these two typical functions are implemented by recourse to a first interface stage for ensuring, as already mentioned, triggering threshold value compatibility (TTL/CMOS), followed by a phase inverting stage (inverter) (IN.) for resetting the correct phase of the signal. The latter is then presented to the input of a first stage ("master" stage) of a double stage "master-slave" memory circuit, e.g. a JK flip-flop.
The input gate of the "master" stage, as well as the transfer gate to the "slave" stage, are controlled by a system's clock through suitable switches.
Such an input circuit of a CMOS circuitry may be represented by the diagram of FIG. 1; the "master" and "slave" stages being identified by the respective dashline squares, M for the "master" stage and S for the "slave" stage.
A clock signal drives the switches SW in a synchronous mode and in phase opposition among them according to the following scheme:
and vice versa.
The operation of such a circuit is well known. Typically, with the descending front (leading edge) of the clock signal, the output data is acquired by the first stage (M) (i.e. SW1 ON; SW2 OFF; SW1' OFF and SW2' ON) and with the subsequent raising front (or trailing edge) of the clock signal, the data is transferred to, and memorized by, the second stage (S) (i.e. SW1 OFF; SW2 ON; SW1' ON and SW2' OFF).
The most commonly used circuits for implementing a TTL/CMOS input interface stage are:
a Schmidt trigger with triggering threshold between the maximum voltage relative to the low logic state (0) and the minimum voltage relative to the high logic state (1); or a comparator circuit with a definite hysteresis capable of allowing the input voltage to drop to the V.sub.SS value.
The circuit diagram of a CMOS Schmidt trigger is shown in FIG. 2.
A CMOS hysteresis comparator circuit wherein the input voltage may drop to the V.sub.SS voltage, is shown by the circuit diagram of FIG. 3.
In any case, by taking into consideration the time behavior of the CMOS input circuit (which may be identified as terminating at the output of the "master" stage),it may be observed that the data presented to the CMOS input circuit will be present at the output of the M stage after a certain period of time corresponding to the sum of the delays introduced by the various stages. This time behavior of the input circuit is indicated by the diagram of FIG. 4.
Clearly the delay introduced is given by: EQU t-t1+t2+t3-t4
where:
Such delays pose naturally limitations to the performance of the circuit in so as the minimum duration of the data (signal) at the input must be greater than the sum of t1+t2+t3 with obvious negative reflections on the transfer speed of data within the CMOS circuit.